ALL ENTITY CNTRL_FSM_Tb -vhd IS END CNTRL_FSM_TB_vhd ĪRCHITECTUTER behavior OF CNTRL_FSM_TB -vhd IS - Component Declaration for the Unit Under Test (UUT) COMPONENT CNTRL_FSMĪDDR : OUT std_logic_vector ( 3 downto 0 ) Ī_IN : OUT std_logic_vector ( 3 downto 0 ) ī_IN : OUT std_logic_vector ( 3 downto 0 ) OP_CODE : std_logic_vector ( 3 downto 0 ) - opcodeĪ_IN : std_logic_vector ( 3 downto 0 ) -A operandī_IN : std_logic_vector ( 3 downto 0 ) -B operandĮxp out : std_logic_vector ( 3 downto 0 ) - expected output End record end MY_CALC_PAk LIBRARY ieee USE ieee. Library IEEE Use IEEE.STD_CALC_PAK is Package MY_CALC_PAK is Type MY_RECORD is Record OUT_REG : regis port map ( rst, clk, enable, xsub, result ) ĭ_o <= result end gcd_arc. X_SUB : subtractor port map ( rst, comparison, xreg, yreg, xsub, ysub ) U_COMP : comparator port map ( rst, xreg, yreg, comparison ) Y_REG : regis port map ( rst, clk, yld, ymux, yreg ) X_REG : regis port map ( rst, clk, xld, xmux, xreg ) Y_MUX : mux port map ( rst, ysel, y_i, ysub, ymux ) X_MUX : mux port map ( rst, xsel, x_i, xsub, xmux )
TOFSM : fsm port map ( rst, clk, go_i, comparison,Įnable, xsel, ysel, xld, yld ) - Datapath Output : out std_logic_vector ( 3 downto 0 ) ) end component signal xld, yld, xsel, ysel, enable : std_logic signal comparison : std_logic_vector ( 1 downto 0 ) signal result : std_logic_vector ( 3 downto 0 ) signal xsub, ysub, xmux, ymux, xreg, yreg : std_logic_vector ( 3 downto 0 ) begin - doing structure modeling here - FSM controller Input : in std_logic_vector ( 3 downto 0 )
Xout, yout : out std_logic_vector ( 3 downto 0 ) ) end component component regis is port ( rst, clk, load : in std_logic Output : out std_logic_vector ( 1 downto 0 ) ) end component component subtractor is port ( rst : in std_logic Ĭmd : in std_logic_vector ( 1 downto 0 ) X, y : in std_logic_vector ( 3 downto 0 ) Output : out std_logic_vector ( 3 downto 0 ) ) end component component comparator is port ( rst : in std_logic X_i, y_i : in std_logic_vector ( 3 downto 0 ) ĭ_o : out std_logic_vector ( 3 downto 0 ) ) end gcd architecture gcd_arc of gcd is component fsm is port ( rst, clk, proceed : in std_logic Ĭomparison : in std_logic_vector ( 1 downto 0 ) Įnable, xsel, ysel, xld, yld : out std_logic ) end component component mux is port ( rst, sLine : in std_logic all entity gcd is port ( rst, clk, go_i : in std_logic
NState enable enable xld enable enable enable nState <= s0 end case end process end fsm_arc - GCD Calculator: top level design using structural modeling - FSM + Datapath (mux, registers, subtracter and comparator) - library IEEE use IEEE. Output : out std_logic_vector ( 3 downto 0 ) ) end mux architecture mux_arc of mux is begin process ( rst, sLine, load, result ) begin if ( rst = ' 1' ) then Load, result : in std_logic_vector ( 3 downto 0 ) all entity mux is port ( rst, sLine : in std_logic Component: MULTIPLEXOR - library IEEE use IEEE.
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